Phase-locked loop circuit and data reproduction apparatus

ABSTRACT

This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit  33  having an edge switching means  4  which controls the phase comparator  1 . The phase comparator  1  inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

FIELD OF THE INVENTION

The present invention relates to a phase-locked loop circuit (PLL) fordigital signals and a control method for a data reproduction apparatus,and more particularly, to a phase-locked loop circuit and a datareproduction apparatus having such a structure that can adjust a slicelevel of a comparator and a phase of a PLL independently.

BACKGROUND OF THE INVENTION

Generally, a circuit for reproducing digital data from an optical discbinarizes a signal from the disc by means of a comparator, and thengenerates a bit synchronous clock by means of a phase-locked loopcircuit (hereinafter, referred to as PLL). In order to reduce a phaseshift between the data signal and the bit synchronous clock, which ishere called jitter, this reproduction circuit has a circuit foradjusting a slice level of the comparator and a phase of the PLL in anearlier time by a jitter detection means or the like. However, theseadjustments for the slice level of the comparator and the phase of thePLL cannot be performed independently, without being affected with eachother.

FIG. 5 is a diagram showing an example of a data reproduction apparatushaving such construction. The conventional data reproduction apparatusshown in FIG. 5 includes a comparator 31, a PLL 35 that receives anoutput (data) from the comparator 31, and a phase shift detection means34. The comparator 31 is provided with a slice level adjustment circuit32. The PLL 35 includes a phase comparator 1, a phase adjustment circuit5, a charge pump 2, and a voltage controlled oscillator (hereinafter,referred to also as a VCO) 3.

Hereinafter, an operation of the data reproduction apparatus will bedescribed.

The comparator 31 receives a signal RF from a recording medium such asan optical disc, and binarizes the signal RF to output a binarizedsignal to the PLL 35 in the latter stage. Here, the slice level that isto be a threshold for the comparator 31 is adjusted by the slice leveladjustment circuit 32 so as to minimize the amount of jitter (the phaseshift between the data signal and the bit synchronous clock), in view ofthe amount of phase difference between the comparator output (data) anda phase-locked clock CLK.

The PLL 35 generates a clock CLK from the binarized signal (data) thatis outputted from the comparator 31, and outputs the generated clockCLK. Here, the phases of the phase-locked clock CLK that is outputtedfrom the VCO 3 and the data from the comparator 31 are compared witheach other, and a control voltage for the VCO 3 is decided by means ofthe charge pump 2, and fed back to lock the phase.

The phase adjustment circuit 5 controls the amount of current in thecharge pump 2 to prevent a phase difference from occurring when aninclination of a rising edge and an inclination of a falling edge of aPLL-generated clock become different from each other due to thedifference in the amount of current between a PMOS transistor and a NMOStransistor constituting the charge pump 2. The amount of current isadjusted, for example, by measuring the amount of jitter to minimize thesame.

FIG. 6 is a timing chart of the conventional data reproduction apparatushaving the above-mentioned structure.

In order to increase the frequency of the phase comparison and improvethe accuracy in the phase locking, the phase comparator 1 thatconstitutes the PLL 35 detects both of rising and falling edges of thedata, and compares the respective edges with one edge (rising or fallingedge) of the clock CLK. In the aforementioned structure in which the PLL35 always performs the phase adjustment with the output from thecomparator 31 whose slice level has been adjusted, the timing of thefalling of the data changes according to duty variations resulting fromthe slice level adjustment for the data that is outputted from thecomparator 31 as shown in FIG. 6, and accordingly the PLL is unfavorablylocked so that the phase of a rising edge is also shifted. Thus, it isrequired to adjust the phase of the data every time when the slice levelis adjusted. That is, the phase adjustment for the data cannot beperformed before the adjustment of the slice level.

Further, in a state where neither the duty nor the phase is adjusted, itcannot be decided whether the phase shift between the data and the CLKis caused by the phase of the data or the duty. Therefore, it isimpossible to perform only the duty correction according to the slicelevel adjustment, before performing the phase adjustment.

To be more specific, in cases of employing the phase comparator thatperforms the detection of both edges, it is impossible to perform one ofthe slice level adjustment and the phase adjustment independently inadvance. Therefore, according to the prior art, the optimum slice leveland phase must be decided on the basis of all combinations as to the twoadjustment patterns.

When there are X possible increments in the slice level adjustment and Ypossible increments in the phase adjustment, there are X*Y possibleadjustment patterns in the entire data reproduction apparatus. Forexample when X and Y are 8 bits, i.e., there are 256 increments,respectively, there are 65,536 increments on the whole, and thus theprocessing time required for the adjustment becomes quite long. Theinitial adjustment including the jitter correcting control in this datareproduction apparatus is performed at each start of a disc, while itcomes to be more difficult to increase the efficiency in the wholeapparatus including other functional blocks, as the rotation speed ofthe optical disc is particularly increased.

Since the conventional phase-locked loop circuit and the control methodfor the data reproduction apparatus are constructed as described above,and the locking operation in the PLL varies depending on different slicelevels of the comparator, the adjustment of the slice level and thephase of the PLL cannot be performed independently without beingaffected with each other, whereby the time required for the initialadjustment in the data reproduction apparatus cannot be reduced.

SUMMARY OF THE INVENTION

The present invention has for its object to provide a phase-locked loopcircuit and a data reproduction apparatus, which can reduce a processingtime that is required for initial adjustment in the data reproductionapparatus.

Other objects and advantages of the present invention will becomeapparent from the detailed description and specific embodimentsdescribed are provided only for illustration since various additions andmodifications within the spirit and scope of the invention will beapparent to those of skill in the art from the detailed description.

According to a 1st aspect of the present invention, there is provided aphase-locked loop circuit comprising: a phase comparator for comparingphases of both rising and falling edges of binarized data with a phaseof a bit synchronous clock; a charge pump for generating a controlvoltage from an output of the phase comparator; a voltage controlledoscillator for generating the bit synchronous clock from an output ofthe charge pump; and an edge switching means for controlling the phasecomparator to perform switching between a comparison result as to onlythe rising or falling edge of the binarized data and a comparison resultas to both of the edges, in the phase comparison between the binarizeddata and the bit synchronous clock by the phase comparator, and tooutput a selected result. Therefore, when this phase-locked loop circuitis incorporated into a data reproduction apparatus, an edge to becompared by the phase comparator can be changed, thereby adjusting theduty of the data signal without affecting a phase shift between the datasignal and the bit synchronous clock, and further only the phase shiftcan be adjusted without depending on the duty.

According to a 2nd aspect of the present invention, in the phase-lockedloop circuit of the 1st aspect, the phase comparator comprises: a firstphase comparator for detecting the falling edge of the binarized data;and a second phase comparator for detecting the rising edge of thebinarized data, and the edge switching means performs the phasecomparison as to the both edges of the binarized data by using an OR ofthe results from the two phase comparators, and performs the phasecomparison as to one of the edges by selecting one of the outputs fromthe two phase comparators and outputting the selected output. Therefore,when this phase-locked loop circuit is incorporated into a datareproduction apparatus, an edge to be compared by the phase comparatorcan be changed, thereby adjusting the duty of the data signal withoutaffecting a phase shift between the data signal and the bit synchronousclock. Further, the adjustment of only the phase shift without dependingon the duty can be realized by a simple construction and withoutrequiring large circuit modification.

According to a 3rd aspect of the present invention, in the phase-lockedloop circuit of the 1st aspect, the phase comparator comprises: a firstphase comparator for detecting the falling edge of the binarized data;and a second phase comparator for detecting the rising edge of thebinarized data, and the edge switching means performs the phasecomparison as to the both edges of the binarized data by using an OR ofoutputs from the two phase comparators, and performs the phasecomparison as to only one edge by fixing an output of one of the twophase comparators by means of a reset signal. Therefore, when thisphase-locked loop circuit is incorporated into a data reproductionapparatus, an edge to be compared by the phase comparator can bechanged, thereby adjusting the duty of the data signal without affectinga phase shift between the data signal and the bit synchronous clock.Further, the adjustment of only the phase shift without depending on theduty can be realized by a simpler construction and without requiringlarge circuit modification.

According to a 4th aspect of the present invention, there is provided adata reproduction apparatus including: a comparator for binarizing areproduction signal from a disc to generate a data signal, a slice leveladjustment circuit for adjusting a slice level of the comparator tocorrect a duty of the data signal, a phase-locked loop circuitcomprising: a phase comparator for comparing phases of both rising andfalling edges of the binarized data with a phase of a bit synchronousclock; a charge pump for generating a control voltage from an output ofthe phase comparator; a voltage controlled oscillator for generating thebit synchronous clock from an output of the charge pump; and an edgeswitching means for controlling the phase comparator to performswitching between a comparison result as to only the rising or fallingedge of the binarized data and a comparison result as to both of theedges, in the phase comparison between the binarized data and the bitsynchronous clock by the phase comparator, and to output a selectedresult, a phase adjustment circuit for controlling the charge pumpincluded in the phase-locked loop circuit to correct the phase, and aphase shift detection means for controlling the duty correction and thephase correction. Therefore, the duty of the data signal can be adjustedwithout affecting a phase shift between the data signal and the bitsynchronous clock, and further only the phase shift can be adjustedwithout depending on the duty.

According to a 5th aspect of the present invention, in the datareproduction apparatus of the 4th aspect, when there are X kinds ofphase adjustment values and Y kinds of slice level adjustment values,one of the X kinds of phase adjustment values which minimizes a phaseshift is selected, and thereafter one of the Y kinds of slice leveladjustment values which optimizes the duty is selected. Therefore, thephase comparison as to one edge is performed only at the phaseadjustment of the data reproduction apparatus, thereby reducing aprocessing time that is required for the control.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a conceptual structure of aphase-locked loop circuit (PLL) according to the present invention.

FIG. 2 is a block diagram illustrating a specific structure of aphase-locked loop circuit (PLL) according to a first embodiment of thepresent invention.

FIG. 3 is a block diagram illustrating a specific structure of aphase-locked loop circuit (PLL) according to a second embodiment of thepresent invention.

FIG. 4 is a block diagram illustrating a structure of a datareproduction apparatus according to a third embodiment of the presentinvention.

FIG. 5 is a block diagram illustrating a structure of a prior art datareproduction apparatus.

FIG. 6 is a timing chart of the prior art reproduction apparatus.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[Embodiment 1]

Hereinafter, a phase-locked loop circuit and a control method for a datareproduction apparatus according to a first embodiment of the presentinvention will be described with reference to the drawings

FIG. 1 is a block diagram illustrating a phase-locked loop circuitaccording to the first embodiment. In FIG. 1, a phase-locked loopcircuit 33 includes a phase comparator 1, a charge pump 2, and a voltagecontrolled oscillator (VCO) 3. The phase comparator 1 is provided withan edge switching means 4. In this figure, a comparator that outputs aninput binarized signal (data) is not shown.

The phase comparator 1 including the edge switching means performs phasecomparison between a rising edge of the input binarized signal data anda bit synchronous clock CLK that is generated by the VCO 3, phasecomparison between a falling edge of the input binarized signal data andthe bit synchronous clock CLK, and phase comparison between both edgesof the input binarized signal data and the bit synchronous clock CLK,and then switches the result of the phase comparison to output the same.Then, the charge pump 2 outputs a control voltage to the VCO 3 accordingto the phase comparison result.

The phase comparator 1 can change an edge detected in the inputbinarized signal (data) by means of the edge switching means 4. That is,the phase comparator 1 can switch the detection timing between a case ofdetecting only a rising or falling edge of the input binarized signal(data) and a case of detecting both of the edges.

FIG. 2 shows a practical example of the edge switching means 4 and thephase comparator 1. In FIG. 2, a phase-locked loop circuit 33 a includesthe phase comparator 1 that is constituted by a phase comparator A (11)and a phase comparator B (12), and the edge switching means 4 that isconstituted by an OR circuit 13 and a switch 14.

One of the two phase comparators A (11) and B (12) (for example, phasecomparator B) performs phase comparison between a rising edge of thedata and the bit synchronous clock CLK, while the other comparator (forexample, phase comparator A) performs phase comparison between a fallingedge of the data and the bit synchronous clock CLK. The results of thetwo phase comparisons are ORed by the OR circuit 13 of the latter stage,to realize the phase comparison with the both edges of the data.Further, by providing the switch 14, only the result of one of the phasecomparators, i.e., the result of the phase comparison with one edge canbe selected without being passed through the OR circuit 13.

According to the first embodiment, the two phase comparators 11 and 12of a type that performs the phase comparison between the falling edge ofthe input binarized signal (data) and the bit synchronous clock CLK, anda type that performs the phase comparison between the rising edge of theinput binarized signal (data) and the bit synchronous clock CLK areprovided as the phase comparator 1 that performs comparison between theinput binarized signal (data) and the bit synchronous clock (CLK).Further, the OR circuit 13 that obtains an OR of the respective outputsof the comparators, and the switch 14 that switches between the outputof the OR circuit 13 and the output of the phase comparator 11 or 12(here, the phase comparator 12) are provided. Therefore, when the phaseadjustment for the PLL is to be performed, the switch 14 is activated sothat the edge detection in the phase comparator 1 is performed to selectonly the rising edge. On the other hand, when the adjustment of theslice level is to be performed, the output of the OR circuit 13 isemployed to perform the phase comparisons with the both edges by thephase comparators 11 and 12. In this way, the phase of the PLL and theduty of the comparator can be adjusted independently.

In this first embodiment, the output of the phase comparator B (12) isconnected to the switch 14, while the output of the phase comparator A(11) may be connected to the switch 14 so that the edge detection in thephase comparator 1 is performed to select only the falling edge.

[Embodiment 2]

A phase-locked loop circuit according to a second embodiment of thepresent invention will be described. FIG. 3 is a block diagramillustrating a structure of the phase-locked loop circuit according tothe second embodiment. In FIG. 3, the same reference numerals as thosein FIG. 2 denote the same or corresponding parts. The phase comparator 1comprises two phase comparators A (21) and B (22), and these comparatorsare connected so as to be combined by an OR circuit 23.

One of the two comparators A (21) and B (22) (for example, phasecomparator B) performs phase comparison between a rising edge of theinput binarized signal (data) and the bit synchronous clock CLK, and theother comparator (for example, phase comparator A) performs phasecomparison between a falling edge of the data and the bit synchronousclock CLK.

The OR circuit 23 obtains an OR of the results of the two phasecomparators as in the first embodiment, whereby the phase comparators Aand B realize the phase comparison with the both edges of the data. Inthis case, one of the two phase comparators (here, the phase comparatorA) is provided with a reset function, and its output is fixed at Low bya reset input R, whereby only the output of the other phase comparator(here, the phase comparator B) is made effective. As a result, the phasecomparison with one edge can be selected.

According to the second embodiment, two phase comparators 21 and 22 of atype that performs the phase comparison between the falling edge of theinput binarized signal (data) and the bit synchronous clock CLK, and atype that performs the phase comparison between the rising edge of theinput binarized signal (data) and the bit synchronous clock CLK areprovided as the phase comparator 1 that performs comparison between theinput binarized signal (data) and the bit synchronous clock CLK.Further, the OR circuit 23 that obtains an OR of the respective outputsof the comparators is provided, and the reset input R that is providedin the phase comparator 21 is inputted to fix the phase comparator 21 atLow, whereby the outputs from the two phase comparators or the outputfrom one of the phase comparators (phase comparator 22) can beselectively obtained by the OR circuit 23. Therefore, when the phaseadjustment for the PLL is to be performed, the reset input R is inputtedto perform the edge detection in the phase comparator 1 so that only therising edge is outputted from the OR circuit 23. On the other hand, whenthe slice level is to be adjusted, an output of the OR circuit 13 thatis an OR of the outputs from the two phase comparators 21 and 22 isemployed to perform the phase comparison with the both edges by thephase comparators 21 and 22. Accordingly, the phase of the PLL and theduty of the comparator can be adjusted independently.

In this second embodiment, the output of the phase comparator A (21) isfixed at Low by using a reset input R, while the output of the phasecomparator B (22) may be fixed at Low by using a reset input R, wherebythe edge detection in the phase comparator 1 is performed so as toselect only a falling edge.

[Embodiment 3]

A data reproduction apparatus according to a third embodiment of thepresent invention will be described. FIG. 4 is a block diagramillustrating a data reproduction apparatus according to the thirdembodiment. In FIG. 4, the same reference numerals as those in FIG. 1denote the same or corresponding parts. The data reproduction apparatusincludes a comparator 31, a slice level adjustment circuit 32, and a PLL33. The PLL 33 includes a phase adjustment circuit 5. The adjustments ofthe slice level and phase are controlled by a phase shift detectionmeans 34.

The comparator 31 receives a signal from a recording medium such as anoptical disc, and binarizes the signal to output a binarized signal(data) to the PLL 33. Here, the slice level that is to be a thresholdfor the comparator 31 is adjusted so as to minimize the amount ofjitter, in view of the amount of phase difference between the data andthe CLK.

The PLL 33 further has a phase adjustment circuit 5 for adjusting theamount of current in the charge pump 2, because the phase difference inthe clock occurs due to the difference in the amount of current betweenthe PMOS and the NMOS in the charge pump 2.

Here, to solve the problem of the prior art, i.e., to eliminate the needfor performing the phase adjustment of the data every time when theslice level is adjusted, the edge switching means 4 performs control forperforming the phase comparison with one edge of the data only at thephase adjustment in the PLL 33.

For example, in the case of the data reproduction apparatus thatgenerates the data and the CLK as shown in the timing chart of FIG. 6,the edge switching means 4 having the structure as shown in the first orsecond embodiment is employed to control the phase comparator 1 foroperating, for example, only with a rising edge of the data only at thephase adjustment in the PLL. Then, after the phase adjustment, the edgeswitching means 4 performs switching to the phase comparison with theboth edges of the data, thereby to adjust the slice level. By doing so,the phase and the duty can be corrected independently and successively,and accordingly the rising edge and the falling edge can be decidedsuccessively.

As described above, when the data reproduction apparatus has thestructure in which the phase adjustment is not affected by the slicelevel adjustment, even in a case where there are 256 possible slicelevel adjustment values and 256 possible phase adjustment values, theentire adjustment in the data reproduction apparatus can be completedonly by 256+256=512 times of measurement. This processing can be carriedout for a time that is shorter than one hundredth of the processing timein the prior art where optimum two adjusted values can be detected onlyby performing jitter measurement on the basis of all combinations as toadjustment patterns so that 65,536 times of the measurement arerequired.

According to the third embodiment, the phase comparator 1 is constructedto perform the phase comparison between a rising edge, a falling edge,or both of the edges of the input binarized signal (data), and the bitsynchronous clock CLK, and the edge switching means 4 controls the phasecomparator 1 for operating only with a rising edge or a falling edge ofthe data to perform the phase adjustment of the PLL, and the edgeswitching means 4 performs switching to the phase comparison with theboth edges of the data after the phase adjustment, to adjust the slicelevel of the comparator 31 by using the slice level adjustment circuit32. Therefore, the slice level adjustment for the comparator 31 and thephase adjustment for the PLL 33 can be performed separately andindependently, whereby the processing time required for the initialadjustment in the data reproduction apparatus can be reduced.

What is claimed is:
 1. A phase-locked loop circuit comprising: a phasecomparator for comparing phases of both rising and falling edges ofbinarized data with a phase of a bit synchronous clock; a charge pumpfor generating a control voltage from an output of the phase comparator;and a voltage controlled oscillator for generating the bit synchronousclock from an output of the charge pump; and the phase comparatorcomprises an edge switching means for switching between a comparisonresult as to only the rising or falling edge of the binarized data and acomparison result as to both of the edges, in the phase comparisonbetween the binarized data and the bit synchronous clock, to output thecomparison result.
 2. The phase-locked loop circuit of claim 1 whereinthe phase comparator comprises: a first phase comparator for performingphase comparison between the falling edge of the binarized data and abit synchronous clock; and a second phase comparator for performingphase comparison between the rising edge of the binarized data and a bitsynchronous clock, and the edge switching means for switching the resultof the phase comparison as to the both edges of the binarized data whichis obtained by an OR of the results from the two phase comparators, andthe result of the phase comparison as to one of the two phasecomparators to output the comparison result.
 3. The phase-locked loopcircuit of claim 1 wherein the phase comparator comprises: a first phasecomparator for detecting the falling edge of the binarized data; and asecond phase comparator for detecting the rising edge of the binarizeddata, and the edge switching means for switching the result of the phasecomparison as to the both edges of the binarized data which is obtainedby an OR of outputs from the two phase comparators, and the result ofthe phase comparison as to only one edge which is obtained by fixing anoutput from one of the two phase comparators by means of a reset signal,to output the comparison result.
 4. A data reproducing apparatusincluding: a comparator for binarizing a reproduction signal from a discto generate a data signal; a slice level adjustment circuit foradjusting a slice level of the comparator to correct a duty of the datasignal; a phase-locked loop circuit comprising: a phase comparatorincluding edge switching means for performing phase comparison between arising edge of the binarized data and a bit synchronous clock, phasecomparison between a falling edge of the binarized data and the bitsynchronous clock, and phase comparison between both edges of thebinarized data and the bit synchronous clock, switching the result ofthe phase comparison, and outputting the selected result; a charge pumpfor generating a control voltage from an output of the phase comparator;and a voltage controlled oscillator for generating the bit synchronousclock from an output of the charge pump; a phase adjustment circuit forcontrolling the charge pump included in the phase-locked loop circuit tocorrect the phase; and a phase shift detection means for controlling theduty correction and the phase correction.
 5. The data reproductionapparatus of claim 4 wherein when there are X kinds of phase adjustmentvalues and Y kinds of slice level adjustment values, one of the X kindsof phase adjustment values which minimizes a phase shaft is selected,and thereafter one of the Y kinds of slice level adjustment values whichoptimizes the duty is selected.